Semiconductor device

ABSTRACT

The semiconductor device according to the present invention includes: a semiconductor layer made of SiC; an impurity region formed by doping the semiconductor layer with an impurity; and a contact wire formed on the semiconductor layer in contact with the impurity region, while the contact wire has a polysilicon layer in the portion in contact with the impurity region, and has a metal layer on the polysilicon layer.

CROSS-REFERENCE TO RELATED APPLICATION

More than one reissue application has been filed for U.S. Pat. No.9,293,575. The reissue applications are Reissue application Ser. No.15/933,357, now U.S. Pat. No. RE48,072. This application is a reissue ofU.S. patent application Ser. No. 13/364,416 (U.S. Pat. No. 9,293,575),issued on Mar. 22, 2016, which is a divisional of application Ser. No.12/654,621 filed on Dec. 24, 2009. Furthermore, this application claimsthe benefit of priority of Japanese applications 2008-330317 filed onDec. 25, 2008, 2008-334480 filed on Dec. 26, 2008, and 2009-293361 filedon Dec. 24, 2009. The disclosures of these prior U.S. and Japaneseapplications are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device employing SiC.

2. Description of Related Art

In recent years, employment of SiC (silicon carbide) as thenext-generation power device material implementing low on-resistance hasbeen examined.

A trench gate structure is known as a structure for refining a powerdevice and reducing on-resistance. For example, a power MOSFET employingthe trench gate structure is increasingly forming the mainstream.

FIG. 15 is a schematic sectional view of a conventional SiCsemiconductor device having a trench gate VDMOSFET.

A semiconductor device 201 includes an N⁺-type SiC substrate 202 formingthe base of the semiconductor device 201. An N⁻-type epitaxial layer 203made of SiC (silicon carbide) doped with an N-type impurity in a lowerconcentration than the SiC substrate 202 is laminated on an Si surface(a silicon surface) of the SiC substrate 202. A base layer portion ofthe epitaxial layer 203 forms an N⁻-type drain region 204 maintaining astate after epitaxy. In the epitaxial layer 203, a P-type body region205 is formed on the drain region 204 in contact with the drain region204.

A gate trench 206 is dug down in the epitaxial layer 203 from a surface217 (an Si surface) thereof. The gate trench 206 passes through the bodyregion 205 in the thickness direction, and the deepest portion (a bottomsurface 216) thereof reaches the drain region 204.

A gate insulating film 207 made of SiO₂ is formed in the gate trench206, to cover the overall regions of the inner surfaces of the gatetrench 206.

A gate electrode 208 is embedded in the gate trench 206 by filling upthe inner side of the gate insulating film 207 with a polysiliconmaterial doped with an N-type impurity in a high concentration.

On a surface layer portion of the epitaxial layer 203, N⁺-type sourceregions 209 are formed on both sides of the gate trench 206 in adirection (the right-and-left direction in FIG. 15) orthogonal to thegate width. The source regions 209 extend along the gate trench 206 in adirection along the gate width, and bottom portions thereof are incontact with the body region 205.

The epitaxial layer 203 is further provided with P⁺-type body contactregions 210 passing through central portions of the source regions 209in the direction orthogonal to the gate width from the surface 217thereof to be connected to the body region 205.

An interlayer dielectric film 211 made of SiO₂ is laminated on theepitaxial layer 203. A source wire 212 is formed on the interlayerdielectric film 211. The source wire 212 has a nickel silicide layer 218in contact with the source regions 209 and the body contact regions 210through a contact hole 213 formed in the interlayer dielectric film 211and an aluminum layer 219 formed on the nickel silicide layer 218.

A drain wire 215 is formed on the rear surface (a carbon surface: a Csurface) of the SiC substrate 202. The drain wire 215 has a nickelsilicide layer 220 in contact with the SiC substrate 202 and an aluminumlayer 221 formed on the nickel silicide layer 220.

In order to form the source wire 212, Ni is first deposited bysputtering on the surfaces (the surfaces of the source regions 209 andthe body contact regions 210) of regions (impurity regions) of theepitaxial layer 203 doped with impurities. Then, Ni is silicified byreacting with Si contained in SiC through a heat treatment at a hightemperature (about 1000° C., for example), to be brought into ohmiccontact with the impurity regions. Thus, the nickel silicide layer 218is formed. Thereafter Al is deposited on the nickel silicide layer 218by sputtering. Thus, the aluminum layer 219 is formed, to form thesource wire 212. The drain wire 215 is also formed by a method similarto that for the source wire 212.

SUMMARY OF THE INVENTION

When the nickel silicide layer 218 is formed, carbon (C) remaining inSiC is deposited on the surface of the nickel silicide layer 218 and inthe vicinity of the interfaces between the nickel silicide layer 218 andthe impurity regions, to form a carbon layer containing a large quantityof C. The carbon layer is so poor in adhesiveness to a metal or SiC thatthe nickel silicide layer 218 is easily peeled from the aluminum layer219 or the impurity regions. Such a disadvantage also applies to thedrain wire 215.

An object of the present invention is to provide a semiconductor devicecapable of improving connection reliability of a contact wire whileensuring ohmic contact between the contact wire and an impurity regionin SiC.

The foregoing and other objects, features and effects of the presentinvention will become more apparent from the following detaileddescription of the embodiments with reference to the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic sectional view of a semiconductor device accordingto a first embodiment of the present invention.

FIGS. 2A to 2N are schematic sectional views for illustrating a methodof manufacturing the semiconductor device shown in FIG. 1 in step order.

FIGS. 3(a) and 3(b) are schematic plan views of a semiconductor deviceaccording to a second embodiment of the present invention, with FIG.3(a) showing the overall semiconductor device and FIG. 3(b) showing aninner portion thereof in an enlarged manner.

FIG. 4 is a schematic sectional view of the semiconductor deviceaccording to the second embodiment of the preset invention, taken alonga line IV-IV in FIG. 3(b).

FIGS. 5A to 5Q are schematic sectional views for illustrating a methodof manufacturing the semiconductor device shown in FIG. 4 in step order.

FIG. 6 is a graph showing temperature changes in a resistance heatingfurnace.

FIG. 7 is a schematic sectional view for illustrating a modification ofthe semiconductor device shown in FIG. 4.

FIGS. 8(a) and 8(b) are schematic plan views of a semiconductor deviceaccording to a third embodiment of the present invention, with FIG. 8(a)showing the overall semiconductor device and FIG. 8(b) showing an innerportion thereof in an enlarged manner.

FIG. 9 is a schematic sectional view of the semiconductor deviceaccording to the third embodiment of the pre sent invention, taken alonga line IX-IX in FIG. 8(b).

FIGS. 10A to 10N are schematic sectional views for illustrating a methodof manufacturing the semiconductor device shown in FIG. 9 in step order.

FIG. 11 is a schematic sectional view for illustrating a modification ofthe semiconductor device shown in FIG. 9.

FIG. 12 is a schematic sectional view of a planar gate semiconductordevice.

FIGS. 13A to 13L are schematic sectional views for illustrating a methodof manufacturing the semiconductor device shown in FIG. 12 in steporder.

FIGS. 14(a) and 14(b) are SEM images of contact wires according toExample 1 and comparative example 1 respectively.

FIG. 15 is a schematic sectional view of a conventional SiCsemiconductor device having a trench gate VDMOSFET.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

A semiconductor device according to an embodiment of the presentinvention includes: a semiconductor layer made of SiC; an impurityregion formed by doping the semiconductor layer with an impurity; and acontact wire formed on the semiconductor layer in contact with theimpurity region, while the contact wire has a polysilicon layer in theportion in contact with the impurity region, and has a metal layer onthe polysilicon layer.

According to the structure, the impurity region is formed in thesemiconductor layer made of SiC by doping the semiconductor layer withthe impurity. The contact wire is in contact with the impurity region.The contact wire has the polysilicon layer in the portion in contactwith the impurity region, and has the metal layer on the polysiliconlayer.

Polysilicon can form excellent ohmic contact with the region (theimpurity region) of SiC doped with the impurity. Therefore,silicification indispensable for a structure having a metal layerdirectly in contact with an impurity region can be omitted. Thus,formation of a carbon layer can be prevented on the surface of thepolysilicon layer and in the vicinity of the interface between thepolysilicon layer and the impurity region.

Consequently, layer peeling can be suppressed between the polysiliconlayer and the metal layer as well as between the polysilicon layer andthe source region. Thus, connection reliability of the source wire canbe improved.

Preferably, the semiconductor device further includes a gate trench dugdown from the surface of the semiconductor layer, a first conductivitytype body region formed in the semiconductor layer on a side portion ofthe gate trench, a gate insulating film formed on the inner surface ofthe gate trench, and a gate electrode embedded in the gate trenchthrough the gate insulating film, the impurity region is a secondconductivity type source region formed on a surface layer portion of thebody region adjacently to the gate trench, and the contact wire is asource wire in contact with the source region.

According to the structure, the gate trench is dug down from the surfaceof the semiconductor layer. In the semiconductor layer, the firstconductivity type body region is formed on the side portion of the gatetrench. On the surface layer portion of the body region, the secondconductivity type source region is formed adjacently to the gate trench.The source wire is in contact with the source region. The gateinsulating film is formed on the bottom surface and the side surface ofthe gate trench. The gate electrode is embedded in the gate trenchthrough the gate insulating film.

Thus, a trench gate VDMOSFET (Vertical Double Diffused MOSFET) havingsuch a MOS (Metal Oxide Semiconductor) structure that the gate electrode(Metal) is opposed to the body region (Semiconductor) through a portionof the gate insulating film located on the side surface of the gatetrench is formed in the semiconductor device.

In the semiconductor device, the source region is the impurity region,and the source wire is the contact wire. In other words, the source wirehas the polysilicon layer in the portion in contact with the sourceregion. Polysilicon is so excellent in coverage that coverage of thesource wire can be improved by forming the polysilicon layer to fill upa contact hole. Consequently, the connection reliability of the sourcewire can be improved.

The semiconductor layer may further include a first conductivity typebody region formed on a surface layer portion of the semiconductorlayer, a gate insulating film formed on the surface of the semiconductorlayer, and a gate electrode formed on the gate insulating film andopposed to the body region through the gate insulating film, theimpurity region may be a second conductivity type source region formedon a surface layer portion of the body region, and the contact wire maybe a source wire in contact with the source region.

The semiconductor device is the so-called planar gate VDMOSFET, in whichthe gate electrode is not embedded in a trench but formed on the gateinsulating film formed on the surface of the semiconductor layer andopposed to the body region through the gate insulating film.

In the semiconductor device, the source region is the impurity region,and the source wire is the contact wire. In other words, the source wirehas the polysilicon layer in the portion in contact with the sourceregion. Polysilicon is so excellent in coverage that coverage of thesource wire can be improved by forming the polysilicon layer to fill upa contact hole. Consequently, the connection reliability of the sourcewire can be improved.

Preferably, the polysilicon layer is a high-concentration doped layerdoped with an impurity in a concentration of 10¹⁹ to 10²¹ cm⁻³.

According to the structure, the polysilicon layer is thehigh-concentration doped layer, whereby resistance in the contact wirecan be reduced.

Preferably in the semiconductor device, a layer containing titanium isinterposed between the polysilicon layer and the metal layer.

A material containing titanium has excellent adhesiveness with respectto both of a polysilicon material and a metal material. In thesemiconductor device having the layer containing titanium interposedbetween the polysilicon layer and the metal layer, therefore,adhesiveness between the polysilicon layer and the metal layer can beimproved. Consequently, the connection reliability of the contact wirecan be further improved.

Preferably in the semiconductor device, the metal layer has a layercontaining Al, and the layer containing titanium has a structureobtained by laminating a Ti layer and a TiN layer in this order from theside closer to the polysilicon layer.

While Al can be utilized as an impurity for providing the polysiliconlayer with conductivity, the resistance of the polysilicon layerutilized as the source wire may be unstabilized unless Al is mixed intothe polysilicon layer in a proper quantity.

In the structure of the semiconductor device, therefore, the TiN layeris interposed between the layer containing Al and the polysilicon layer,as a barrier layer for preventing diffusion of Al into the polysiliconlayer. Thus, no excessive Al diffuses into the polysilicon layer,whereby the impurity concentration in the polysilicon layer can bestabilized. Consequently, the resistance of the polysilicon layer can bestabilized.

The polysilicon layer may be doped with at least one type of conductiveimpurity selected from a group consisting of B, P, Al and N.

In activation of the body region and the source region or formation ofthe gate insulating film, the semiconductor layer made of SiC may beheated to a temperature of not less than 1200° C., and the following isknown as the background technique related to heating of a semiconductorlayer made of SiC, for example:

More specifically, a MOSFET having a MOS (Metal Oxide Semiconductor)structure formed by an SiC layer having an activated ion region on asurface layer portion thereof, a gate oxide film formed on the surfaceof the SiC layer and a gate electrode formed on the gate oxide film andopposed to the ion region through the gate oxide film, for example, isknown as a semiconductor device employing SiC.

In order to prepare such a MOS structure, impurity ions are firstimplanted into the surface layer portion of the SiC layer, for example.Then, the SiC layer is heated in a resistance heating furnace, wherebythe implanted ions are activated. After the activation of the ions, thegate oxide film is formed on the surface of the SiC layer by feedingoxygen-containing gas in a CVD (Chemical Vapor Deposition) apparatus.Then, the gate electrode is formed on the gate oxide film by sputtering.Thus, a layered structure (the MOS structure) of the gate electrode(Metal), the gate oxide film (Oxide) and the SiC layer (Semiconductor)is produced.

In order to activate the ions in the SiC layer, the SiC layer must beannealed at a temperature of 1600 to 1700° C., for example. In theresistance heating furnace, it takes a long time to heat the SiC layerup to a high temperature range, and hence Si sublimates from the surfaceof the SiC layer by the so-called Si escape, to roughen the surface ofthe SiC layer. Consequently, the interface between the SiC layer and thegate oxide film is irregularized, to reduce channel mobility of theMOSFET.

Therefore, a technique of suppressing surface roughening of the SiClayer by utilizing a high-frequency induction heater for reducing thetime for heating the SiC layer up to the high temperature range andthereafter forming the gate oxide film through a gate oxidation furnaceis employed.

However, such a technique separately requires two apparatuses, i.e., thehigh-frequency induction heater and the gate oxidation furnace, andhence the device cost is disadvantageously increased.

Another technique of forming a carbon film on the surface of the SiClayer in advance of the activation of the ions and preventing the Siescape with the carbon film thereby maintaining planarity on the surfaceof the SiC layer is proposed.

The carbon film is prepared by forming a film containing carbon on thesurface of the SiC layer and heating the film containing carbon in thehigh-frequency induction heater thereby evaporating elements other thancarbon from the film, for example.

According to studies made by the inventors, however, a heatingtemperature for forming the carbon film may be about 1000° C., which islower than the temperature (1600 to 1700° C.) for activating the ions.Therefore, the heating temperature must be controlled in two stages,while it has been recognized difficult to precisely temperature-controlthe high-frequency induction heater.

After the activation of the ions, the carbon film is no longer required.The unrequited carbon film is oxidized and removed with oxidizing gas inan apparatus different from the high-frequency induction heater. Whilethe oxidizing gas may be introduced into the high-frequency inductionheater to remove the carbon film subsequently to the activation of theions, a carbon material is used for a heating element of thehigh-frequency induction heater and hence the carbon material isoxidized when fed with the oxidizing gas. Therefore, a carbon filmremoving apparatus is inevitably additionally required, to unavoidablyincrease the device cost.

In order to attain an object of providing a method of manufacturing asemiconductor device capable of suppressing roughening on the surface ofan SiC layer through simple temperature control without increasing thedevice cost, the inventors have provided the following invention:

More specifically, the method of manufacturing a semiconductor deviceaccording to the invention includes the steps of forming an organicmaterial film on the surface of an SiC layer having a surface layerportion into which ions have been implanted, altering the organicmaterial film into a carbon film by heating the organic material film ina resistance heating furnace after the formation of the organic materialfilm, activating the ions in the SiC layer by heating the SiC layerprovided with the carbon film in the resistance heating furnace,oxidizing and removing the carbon film by introducing oxygen-containinggas into the resistance heating furnace, and forming an oxide film byoxidizing the surface of the SiC layer with the oxygen-containing gas inthe resistance heating furnace continuously after the removal of thecarbon film.

According to the method, the organic material film is heated in theresistance heating furnace after the formation of the organic materialfilm, whereby the organic material film is altered into the carbon film,and the carbon film is formed on the surface of the SiC layer. After theformation of the carbon film, the SiC layer is heated in order toactivate the ions in the SiC layer. Thereafter the carbon film isoxidized and removed by introducing the oxygen-containing gas into theresistance heating furnace. After the removal of the carbon film, thesurface of the SiC layer is oxidized with the oxygen-containing gascontinuously in the resistance heating furnace, so that the surface ofthe SiC layer is oxidized with the oxygen-containing gas and the oxidefilm is formed.

The carbon film is formed on the surface of the SiC layer in advance ofthe heating for activating the ions, whereby Si escape from the surfaceof the SiC layer can be prevented when the SiC layer is heated.Therefore, roughening on the surface of the SiC layer can be suppressed,and planarity on the surface of the SiC layer can be maintained.Consequently, the interface between the SiC layer and the oxide film canbe smoothed, whereby channel mobility of the semiconductor device can beimproved.

Further, the four steps of altering the organic material film into thecarbon film by heating the same, activating the ions by heating the SiClayer, oxidizing and removing the carbon film with the oxygen-containinggas, and forming the oxide film by oxidizing the surface of the SiClayer can be continuously carried out in a single resistance heatingfurnace. No apparatus for removing the carbon film or the like isadditionally required, whereby increase in the device cost can also besuppressed. Further, the resistance heating furnace is so employed thatthe heating temperature for forming the carbon film and that foractivating the ions can be precisely and simply controlled.

The oxygen-containing gas may be gas containing oxygen and nitrogen.When the oxygen-containing gas for forming the oxide film containsoxygen and nitrogen, the channel mobility of the semiconductor devicecan be further improved.

Gas containing NO (nitrogen monoxide), N₂O (dinitrogen oxide) or thelike, for example, can be employed as the gas containing oxygen andnitrogen.

Preferably, the surface of the SiC layer is defined by a (0001) plane,i.e., an Si surface.

As hereinabove described, the inventors have provided the inventionutilizing the resistance heating furnace as the invention related toheating of the semiconductor layer made of SiC.

When the aforementioned invention utilizing the resistance heatingfurnace is applied in the activation of the body region and the sourceregion as well as the formation of the gate insulating film, therefore,functions/effects of the aforementioned invention utilizing theresistance heating furnace can be attained in addition to those of thepresent invention.

Embodiments of the present invention are now described in detail withreference to the attached drawings.

FIG. 1 is a schematic sectional view of a semiconductor device accordingto a first embodiment of the present invention.

A semiconductor device 1 has a structure obtained by arranging aplurality of unit cells of a trench gate VDMOSFET in the form of amatrix. FIG. 1 shows only part of the plurality of unit cells.

The semiconductor device 1 includes an SiC substrate 2 forming the basethereof. The SiC substrate 2 is doped with an N-type impurity in a highconcentration (10¹⁸ to 10²¹ cm⁻³, for example). The SiC substrate 2 hasa surface 21 (an upper surface) formed by an Si surface and a rearsurface (a lower surface) 22 formed by a C surface.

An N⁻-type epitaxial layer 3 made of SiC (silicon carbide) doped with anN-type impurity in a lower concentration than the SiC substrate 2 islaminated on the surface 21 of the SiC substrate 2. The epitaxial layer3 formed on the surface 21, i.e., the Si surface, is grown with a majorgrowth surface formed by an Si surface. Therefore, the epitaxial layer 3has a surface 31 formed by the Si surface.

A portion (a base layer portion) of the epitaxial layer 3 opposite to aportion (a surface layer portion) on the side of the Si surface forms anN⁻-type drain region 4 entirely maintaining a state after epitaxy. Thedrain region 4 has an N-type impurity concentration of 10¹⁵ to 10¹⁷cm⁻³, for example.

On the other hand, a P-type body region 5 is formed on the surface layerportion of the epitaxial layer 3. The body region 5 is in contact withthe drain region 4. The body region 5 has a P-type impurityconcentration of 10¹⁶ to 10¹⁹ cm⁻³, for example.

A gate trench 6 is dug down in the epitaxial layer 3 from the surface 31thereof. A plurality of such gate trenches 6 (not shown in FIG. 1) areformed at regular intervals to parallelly extend in the same direction(a direction parallel to the plane of FIG. 1: the direction mayhereinafter be referred to as a “direction along the gate width”),thereby forming a striped structure, for example.

Each gate trench 6 has planar side surfaces 7 opposed to each other atan interval and orthogonal to the surface 31 respectively and a bottomsurface 8 having a portion parallel to the surface 31. The gate trench 6passes through the body region 5 in the thickness direction, and thedeepest portion (the bottom surface 8) thereof reaches the drain region4.

A gate insulating film 9 made of SiO₂ is formed on the inner surfaces ofthe gate trench 6 and the surface 31 of the epitaxial layer 3, to coverthe overall regions of the inner surfaces (the side surfaces 7 and thebottom surface 8) of the gate trench 6. In the gate insulating film 9,the thickness of a portion (an insulating film bottom portion 11)located on the bottom surface 8 is smaller than that of portions(insulating film side portions 10) located on the side surfaces 7. Forexample, the ratio (thickness of insulating film bottom portion11/thickness of insulating film side portion 10) of the thickness of theinsulating film bottom portion 11 to that of the insulating film sideportions 10 is 0.1 to 0.8. More specifically, the thickness of theinsulating film side portions 10 is 400 to 600 Å and that of theinsulating film bottom portion 11 is 200 to 300 Å, for example.

A gate electrode 12 is embedded in the gate trench 6 by filling up theinner side of the gate insulating film 9 with a polysilicon materialdoped with an N-type impurity in a high concentration.

On a surface layer portion of the body region 5, N⁺-type source regions13 are formed on both sides of the gate trench 6 in a direction (theright-and-left direction in FIG. 1) orthogonal to the gate width. Thesource regions 13 are doped with an N-type impurity in a higherconcentration than the drain region 4. The source regions 13 have anN-type impurity concentration of 10¹⁸ to 10²¹ cm⁻³, for example. Thesource regions 13 extend in the direction along the gate width onpositions adjacent to the gate trench 6, and the bottom portions thereofare in contact with the body region 5 from the side of the surface 31 ofthe epitaxial layer 3.

The epitaxial layer 3 is provided with P⁺-type body contact regions 14pas sing through central portions of the source regions 13 in thedirection orthogonal to the gate width from the surface 31 thereof to beconnected to the body region 5. The body contact regions 14 are dopedwith a P-type impurity in a higher concentration than the body region 5.The body contact regions 14 have a P-type impurity concentration of 10¹⁸to 10²¹ cm⁻³, for example.

In other words, the gate trench 6 and the source regions 13 arealternately provided in the direction orthogonal to the gate width, andextend in the direction along the gate width respectively. Boundariesbetween the unit cells adjacent to one another in the directionorthogonal to the gate width are set on the source regions 13 along thesource regions 13. At least one or more body contact regions 14 areprovided over two unit cells adjacent to each other in the directionorthogonal to the gate width. The boundaries between the unit cellsadjacent to one another in the direction along the gate width are so setthat the gate electrode 12 included in each unit cell has a constantgate width.

An interlayer dielectric film 15 made of SiO₂ is laminated on theepitaxial layer 3. A contact hole 16 exposing the surfaces of the sourceregions 13 and the body contact regions 14 is formed in the interlayerdielectric film 15 and the gate insulating film 9.

A source wire 17 is formed on the interlayer dielectric film 15. Thesource wire 17 is in contact (electrically connected) with the sourceregions 13 and the body contact regions 14 through the contact hole 16.The source wire 17 has a polysilicon layer 18 in the portion in contactwith the source regions 13 and the body contact regions 14, and has ametal layer 20 on the polysilicon layer 18.

The polysilicon layer 18 is a doped layer made of doped polysilicondoped with an impurity, and preferably a high-concentration doped layerdoped with the impurity in a high concentration of 10¹⁹ to 10²¹ cm⁻³,for example. The impurity for forming the polysilicon layer 18 as thedoped layer (including the high-concentration doped layer) can beprepared from an N-type impurity such as P (phosphorus) or As (arsenic)or a P-type impurity such as B (boron). The polysilicon layer 18 fillsup the contact hole 16. The thickness of the polysilicon layer 18 is5000 to 10000 Å, for example, depending on the depth of the contact hole16.

The metal layer 20 is made of aluminum (Al), gold (Au), silver (Ag) orcopper (Cu), an alloy thereof, or a metal material containing the same,for example. The metal layer 20 forms the outermost layer of the sourcewire 17, and a metal wire or the like, for example, is connected(bonded) thereto. The thickness of the metal layer 20 is 1 to 5 μm, forexample.

In the source wire 17, an intermediate layer 19 containing titanium isinterposed between the polysilicon layer 18 and the metal layer 20. Theintermediate layer 19 is formed by a single layer containing titanium(Ti) or a plurality of layers including the layer. The layer containingtitanium can be prepared from titanium, titanium nitride or the like.The thickness of the intermediate layer 19 is 200 to 500 Å, for example.

The aforementioned source wire 17 having the polysilicon layer 18, theintermediate layer 19 and the metal layer 20 preferably has a multilayerstructure (Poly-Si/Ti/TiN/Al) obtained by successively laminatingpolysilicon (the polysilicon layer 18), titanium (the intermediate layer19), titanium nitride (the intermediate layer 19) and aluminum (themetal layer 20).

A drain wire 23 is formed on the rear surface 22 of the SiC substrate 2.The drain wire 23 is in contact (electrically connected) with the SiCsubstrate 2. The drain wire 23 has a polysilicon layer 24 in the portionin contact with the SiC substrate 2, and has a metal layer 26 on thepolysilicon layer 24.

The polysilicon layer 24 can be made of a material similar to thatconstituting the aforementioned polysilicon layer 18. The thickness ofthe polysilicon layer 24 is 1000 to 2000 Å, for example.

The metal layer 26 can be made of a material similar to thatconstituting the aforementioned metal layer 20. The metal layer 26 formsthe outermost layer of the drain wire 23, and is bonded to a die pad ofa lead frame when the SiC substrate 2 is bonded to the die pad, forexample. The thickness of the metal layer 26 is 0.5 to 1 μm, forexample.

In the drain wire 23, an intermediate layer 25 containing titanium isinterposed between the polysilicon layer 24 and the metal layer 26. Theintermediate layer 25 can be made of a material similar to thatconstituting the aforementioned intermediate layer 19.

A gate wire 27 is in contact (electrically connected) with the gateelectrode 12 through a contact hole (not shown) formed in the interlayerdielectric film 15.

A prescribed voltage (a voltage of not less than a gate thresholdvoltage) is applied to the gate wire 27 while a prescribed potentialdifference is caused between the source wire 17 and the drain wire 23(between a source and a drain), whereby a channel is formed in thevicinity of the interface between the body region 5 and the gateinsulating film 9 due to an electric field from the gate electrode 12.Thus, a current flows between the source wire 17 and the drain wire 23,and the VDMOSFET is turned on.

FIGS. 2A to 2N are schematic sectional views for illustrating a methodof manufacturing the semiconductor device 1 shown in FIG. 1 in steporder.

First, an SiC crystal is grown on the surface 21 (the Si surface) of theSiC substrate 2 by epitaxy such as CVD (Chemical Vapor Deposition), LPE(Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping thesame with an impurity, as shown in FIG. 2A. Thus, the N⁻-type epitaxiallayer 3 is formed on the SiC substrate 2. Then, a P-type impurity isimplanted into the epitaxial layer 3 from the surface 31 thereof. Whilethe implantation conditions vary with the type of the P-type impurity,acceleration energy is 200 to 400 keV, for example.

Thus, a region (a P-type implantation region 28) into which the P-typeimpurity has been implanted is formed on the surface layer portion ofthe epitaxial layer 3, as shown in FIG. 2B. Due to the formation of theP-type implantation region 28, the drain region 4 isolated from theP-type implantation region 28 while maintaining the state after theepitaxy is formed on the base layer portion of the epitaxial layer 3.

Then, a mask 29 made of SiO₂ is formed on the epitaxial layer 3 by CVD,as shown in FIG. 2C. Then, the mask 29 is etched through a photoresistfilm (not shown) into a pattern having openings 30 in regions forforming the body contact regions 14. After the formation of the openings30, a P-type impurity is implanted into the epitaxial layer 3 from thesurface 31 thereof. While the implantation conditions vary with the typeof the P-type impurity, acceleration energy is 30 to 200 keV, forexample. Thus, regions (P⁺-type implantation regions 32) into which theP-type impurity has been implanted in a high concentration are formed ona surface layer portion of the P-type implantation region 28. After theimplantation of the P-type impurity, the mask 29 is removed.

Then, a mask 33 made of SiO₂ is formed on the epitaxial layer 3 by CVD(Chemical Vapor Deposition), as shown in FIG. 2D. Then, the mask 33 isetched through a photoresist film (not shown) into a pattern havingopenings 34 in regions for forming the source regions 13. After theformation of the openings 34, an N-type impurity is implanted into theepitaxial layer 3 from the surface 31 thereof. While the implantationconditions vary with the type of the N-type impurity, accelerationenergy is 30 to 200 keV, for example. After the implantation of theN-type impurity, the mask 33 is removed. Thus, a region (an N⁺-typeimplantation region 35) into which the N-type impurity has beenimplanted in a high concentration is formed on the surface layer portionof the P-type implantation region 28.

Then, the epitaxial layer 3 is heat-treated at a temperature of 1400 to2000° C., for example, as shown in FIG. 2E. Thus, the implanted N- andP-type impurities are activated, whereby the body region 5 is formed onthe surface layer portion 3 of the epitaxial layer 3, while the sourceregions 13 and the body contact regions 14 are formed on the surfacelayer portion of the body region 5.

Then, a mask 36 made of SiO₂ is formed on the overall region of thesurface 31 of the epitaxial layer 3 by CVD or thermal oxidation, asshown in FIG. 2F. The mask 36 may alternatively be made of SiN or thelike through CVD.

Then, the mask 36 is etched through a photoresist film (not shown) intoa pattern having an opening 37 in a region for forming the gate trench6, as shown in FIG. 2G.

Then, mixed gas (SF₆/O₂ gas) containing SF₆ (sulfur hexafluoride) and O₂(oxygen) is introduced into the surface 31 of the epitaxial layer 3through the opening 37, as shown in FIG. 2H. Thus, the epitaxial layer 3is dry-etched from the surface 31 (the Si surface), and the gate trench6 having the bottom surface 8 having the portion (the Si surface)parallel to the surface 31 and the side surfaces 7 orthogonal to the Sisurface is formed. After the formation of the gate trench 6, the mask 36is removed.

Then, the inner surfaces (the side surfaces 7 and the bottom surface 8)of the gate trench 6 and the surface 31 of the epitaxial layer 3 areoxidized by thermal oxidation, as shown in FIG. 2I. The gate trench 6 isformed in the epitaxial layer 3 made of SiC, and hence the oxidation ofthe inner surfaces of the gate trench 6 progresses under the conditionthat the oxidation rate for the bottom surface 8 having the Si surfaceand that for the side surfaces 7 orthogonal to the Si surface satisfythe following relational expression:Oxidation rate for bottom surface 8/oxidation rate for side surface 7<0Thus, the gate insulating film 9 is formed so that the thickness of theportion (the insulating film bottom portion 11) located on the bottomsurface 8 is smaller than that of the portions (the insulating film sideportions 10) located on the side surfaces 7.

Then, a doped polysilicon material is deposited on the epitaxial layer 3by CVD, as shown in FIG. 2J. The deposited polysilicon material isetched back until the etched-back surface is flush with the surface 31of the epitaxial layer 3. Thus, portions of the polysilicon layerlocated outside the gate trench 6 are removed, and the gate electrode 12is formed by the polysilicon material remaining in the gate trench 6.

Then, the interlayer dielectric film 15 made of SiO₂ is laminated on theepitaxial layer 3 by CVD, as shown in FIG. 2K. Then, the interlayerdielectric film 15 and the gate insulating film 9 are so patterned thatthe contact hole 16 exposing the source regions 13 and the body contactregions 14 is formed in the interlayer dielectric film 15 and the gateinsulating film 9.

Then, a polysilicon material 38 is laminated by CVD to fill up thecontact hole 16, as shown in FIG. 2L.

Then, an N- or P-type impurity is implanted into the depositedpolysilicon material, as shown in FIG. 2M. While the implantationconditions vary with the type of the impurity, acceleration energy is 10to 100 keV, for example. Thus, the polysilicon layer 18 doped with theimpurity in a high concentration is formed.

Then, titanium and titanium nitride are deposited in this order on thesurface of the polysilicon layer 18 by a method such as sputtering orvapor deposition to form the intermediate layer 19, as shown in FIG. 2N.Then, aluminum is deposited on the surface of the intermediate layer 19by a method such as sputtering or vapor deposition, to form the metallayer 20. Then, the metal layer 20, the intermediate layer 19 and thepolysilicon layer 18 are worked into a prescribed pattern, to form thesource wire 17. Then, the gate wire 27 connected to the gate electrode12 is formed. Thereafter the drain wire 23 having the polysilicon layer24, the intermediate layer 25 and the metal layer 26 is formed on therear surface 22 of the SiC substrate 2 by a method similar to that forthe source wire 17.

The semiconductor device 1 shown in FIG. 1 is obtained through theaforementioned steps.

In the semiconductor device 1, as hereinabove described, the source wire17 in contact with the source regions 13 and the body contact regions 14has the polysilicon layer 18 in the portion in contact with the sourceregions 13 and the body contact regions 14, and has the metal layer 20on the polysilicon layer 18.

Polysilicon can form excellent ohmic contact with a region (an impurityregion) of SiC doped with an impurity. Therefore, ohmic contact can beformed between the polysilicon layer 18 and the source regions 13 aswell as the body contact regions 14 by depositing the polysiliconmaterial 38 by CVD as hereinabove described and bringing the polysiliconlayer 18 into contact with the source regions 13 and the body contactregions 14.

Therefore, silicification indispensable for a structure having a metallayer directly brought into contact with an impurity region can beomitted. Thus, formation of a carbon layer can be prevented on thesurface of the polysilicon layer 18 and in the vicinity of the interfacebetween the polysilicon layer 18 and the source regions 13 and the bodycontact regions 14.

Consequently, layer peeling can be suppressed between the polysiliconlayer 18 and the metal layer 20 as well as between the polysilicon layer18 and the source regions 13 and the body contact regions 14. Thus,connection reliability of the source wire 17 can be improved.

The source wire 17 is in contact with the source regions 13 and the bodycontact regions 14 through the contact hole 16 of the interlayerdielectric film 15. In the source wire 17, the polysilicon layer 18 madeof the polysilicon material excellent in coverage is formed with thethickness filling up the contact hole 16. Therefore, coverage of thesource wire 17 can be improved. Consequently, the connection reliabilityof the source wire 17 can be further improved. Further, planarity of themetal layer 20 formed on the polysilicon layer 18 can be improved.Consequently, bondability can be improved when the metal wire is bondedto the metal layer 20.

The polysilicon layer 18 is a high-concentration doped layer doped withthe impurity in the high concentration of 10¹⁹ to 10²¹ cm⁻³, whereby theresistance of the source wire 17 can be reduced.

Further, the intermediate layer 19 having the multilayer structure ofthe titanium layer and the titanium nitride layer is interposed betweenthe polysilicon layer 18 and the metal layer 20. A material containingtitanium has excellent adhesiveness with respect to both of apolysilicon material and a metal material. Therefore, the adhesivenessbetween the polysilicon layer 18 and the metal layer 20 can be improved.Consequently, the connection reliability of the source wire 17 can befurther improved.

Functions and effects attained by the drain wire 23 having thepolysilicon layer 24, the intermediate layer 25 and the metal layer 26are similar to those attained by the source wire 17, and hence redundantdescription is omitted.

FIGS. 3(a) and 3(b) are schematic plan views of a semiconductor deviceaccording to a second embodiment of the present invention, with FIG.3(a) showing the overall semiconductor device and FIG. 3(b) showing aninner portion thereof in an enlarged manner.

A semiconductor device 41 according to the second embodiment of thepresent invention is a trench gate power VDMOSFET (an individual device)employing SiC, in the form of a chip square in plan view, for example.The chip-like semiconductor device 41 has a length of about several mmin the right-and-left (vertical) direction in the plane of FIG. 3(a).

The semiconductor device 41 has an SiC substrate 42 and a large numberof unit cells 44 formed on the SiC substrate 42 and partitioned by agate trench 43 latticed in plan view. In other words, the unit cells 44in the form of rectangular parallelepipeds arranged in window portionsof the latticed gate trench 43 respectively are aligned on the SiCsubstrate 42 in the form of a matrix. Each unit cell 44 has a length ofnot more than 10 μm in the right-and-left (vertical) direction in theplane of FIG. 3(b), for example, and a source trench 45, square in planview, dug down from the surface side toward the side of the SiCsubstrate 42 is formed at the center thereof.

A source pad 46 is formed on the surface of the semiconductor device 41.The source pad 46 is generally in the form of a square having outwardlybent four corners in plan view, and formed to generally cover theoverall region of the surface of the semiconductor device 41. A removedregion 47 is formed in the source pad 46 by partially removing the samein a generally square manner in plan view, on a position slightlyleftward in the right-and-left direction in the plane of FIG. 3(a).

A gate pad 48 is arranged on the removed region 47. An interval isprovided between the gate pad 48 and the source pad 46, which areinsulated from each other.

FIG. 4 is a schematic sectional view of the semiconductor device 41according to the second embodiment of the preset invention, taken alonga line IV-IV in FIG. 3(b).

The sectional structure of the semiconductor device 41 is described withreference to FIG. 4. The semiconductor device 4 includes the SiCsubstrate 42 of an N⁺-type (having a concentration of 10¹⁸ to 10²¹ cm⁻³,for example). The SiC substrate 42 has a surface 49 (an upper surface)formed by an Si surface and a rear surface 50 (a lower surface) formedby a C surface.

An N⁻-type epitaxial layer 51 made of SiC having a lower concentration(10¹⁵ to 10¹⁷ cm⁻³, for example) than the SiC substrate 42 is laminatedon the SiC substrate 42. The epitaxial layer 51 as a semiconductor layeris formed on the SiC substrate 42 by the so-called epitaxy. Theepitaxial layer 51 formed on the surface 49, i.e., the Si surface, isgrown on a major growth surface formed by an Si surface. Therefore, asurface 52 of the epitaxial layer 51 formed by the growth is an Sisurface, similarly to the surface 49 of the SiC substrate 42.

On the side of the epitaxial layer 51 closer to the surface 52 (the Sisurface), a P-type body region 53 is provided in the form of a well overa wide range, with a concentration of 10¹⁶ to 10¹⁹ cm⁻³, for example. Aregion of the epitaxial layer 51 closer to the SiC substrate 42 (the Csurface) than the body region 53 forms an N⁻-type drain region 54 (adrift region) maintaining the state after the epitaxy.

In the body region 53, an N⁺-type source region 55 (having aconcentration of 10¹⁸ to 10²¹ cm⁻³, for example) is formed generally onthe overall region of the side closer to the surface 52, while a P⁺-typebody contact region 56 (having a concentration of 10¹⁸ to 10²¹ cm⁻³, forexample) is formed on a side (the lower side) closer to the SiCsubstrate 42 than the source region 55. A large number of such bodycontact regions 56 are provided in the form of a matrix.

Source trenches 45 are formed in the same number as the body contactregions 56 so that each source trench 45 passes through each bodycontact region 56, and the latticed gate trench 43 is formed to surroundeach body contact region 56 provided with the source trench 45. Thus,the large number of unit cells 44 functioning as field-effecttransistors respectively are formed on the epitaxial layer 51. In otherwords, the body contact region 56 is formed to surround thecorresponding source trench 45 and the body region 53 is formed tosurround the body contact region 56 in each unit cell 44. A side of thebody region 53 opposite to the side closer to the body contact region 56is exposed on the side surfaces of the gate trench 43. In the unit cell44, the depth direction of the gate trench 43 corresponds to a gatelength direction, and the peripheral direction of each unit cell 44orthogonal to the gate length direction corresponds to a gate widthdirection.

Both of the source trench 45 and the gate trench 43 pass through thebody region 53 from the surface 52 of the epitaxial layer 51 to reachthe drain region 54, and the depths thereof are identical to each otherin the second embodiment. The distance D₁ between side surfaces 59 and57 of the source trench 45 and the gate trench 43 is 0.5 to 3 μm, forexample. When the distance D₁ is in this range, increase in resistance(on-resistance) can be suppressed when each unit cell 44 is turned on,and an electric field applied to the bottom portion of the gate trench43 can be relaxed.

The gate trench 43 is U-shaped in section, such that both end cornerportions 61 of the bottom portion thereof in a direction (a directionopposed to the adjacent unit cell 44) orthogonal to the gate width arebent toward the side of the drain region 54 and the side surfaces 57opposed to each other and a bottom surface 58 are continuous throughbent surfaces. The source trench 45 is also U-shaped in sectionsimilarly to the gate trench 43, such that the side surfaces 59 opposedto each other and a bottom surface 60 are continuous through bentsurfaces. When the unit cell 44 is turned off, therefore, the electricfield applied to both end corner portions 61 of the bottom portion ofthe gate trench 43 can be dispersed to portions other than both endcorner portions 61, whereby a portion of the gate insulating film 63located on the bottom surface 58 can be prevented from dielectricbreakdown.

A gate insulating film 63 is formed on the inner surfaces of the gatetrench 43, to cover the overall regions thereof. The gate insulatingfilm 63 consists of an oxide film containing nitrogen, such as a siliconoxynitride film formed by thermal oxidation with gas containing nitrideand oxygen, for example. The nitrogen content (the nitrogenconcentration) in the gate insulating film 63 is 0.1 to 10%, forexample.

A gate electrode 66 is embedded in the gate trench 43 by filling up theinner side of the gate insulating film 63 with a polysilicon materialdoped with an N-type impurity in a high concentration.

An interlayer dielectric film 67 made of SiO₂ is laminated on theepitaxial layer 51. A contact hole 68 exposing the surfaces of thesource trench 45 and the source region 55 of each unit cell 44 is formedin the interlayer dielectric film 67 and the gate insulating film 63.

A source wire 69 is formed on the interlayer dielectric film 67. Thesource wire 69 collectively enters the source trench 45 of every unitcell 44 through each contact hole 68, and is in contact with the drainregion 54, the body contact region 56 and the source region 55successively from the bottom side of the source trench 45 in each unitcell 44. In other words, the source wire 69 is common to all unit cells44. An interlayer dielectric film (not shown) is formed on the sourcewire 69, which in turn is electrically connected to the source pad 46(see FIG. 3(a)) through the interlayer dielectric film (not shown). Onthe other hand, the gate pad 48 (see FIG. 3(a)) is electricallyconnected to the gate electrode 66 through a gate wire (not shown) drawnonto the interlayer dielectric film (not shown).

The source wire 69 has a polysilicon layer 70, an intermediate layer 71and a metal layer 72 successively from the side in contact with theepitaxial layer 51.

The polysilicon layer 70 is a doped layer made of doped polysilicondoped with an impurity, such as a high-concentration doped layer dopedwith the impurity in a high concentration of 10¹⁹ to 10²¹ cm⁻³, forexample. The impurity for forming the polysilicon layer 70 as the dopedlayer (including the high-concentration doped layer) can be preparedfrom an N-type impurity such as N (nitrogen), P (phosphorus) or As(arsenic)or a P-type impurity such as Al (aluminum) or B (boron). Thethickness of the polysilicon layer 70 is 5000 to 10000 Å, for example.

According to the second embodiment, the polysilicon layer 70 is formedto cover the overall region of the surface of the unit cell 44 exposedin the contact hole 68, and in contact with the drain region 54, thebody contact region 56 and the source region 55 in the source trench 45.

The layer of the source wire 69 in contact with the drain region 54, thebody contact region 56 and the source region 55 is made of polysilicon,whereby the source wire 69 can be brought into ohmic contact with bothof the body contact region 56 and the source region 55, which arehigh-concentration impurity regions. On the other hand, a heterojunctionhaving a smaller junction barrier than the diffusion potential of a bodydiode 73 (a PN diode formed by junction between the body region 53 andthe drain region 54) intrinsic in the semiconductor device 41 can beformed with respect to the low-concentration drain region 54.

When a current flows to the body diode 73 intrinsic in the semiconductordevice 41, positive holes (holes) moving from the body region 53 to thedrain region 54 recombine with electrons in the drain region 54, and adefect of an SiC crystal in the epitaxial layer 51 may spread in theplane due to the resulting recombination energy. The resistance of thecrystal defect is so high that the crystal defect may hinder an ordinarytransistor operation to increase on-resistance when spreading toward theside of the gate trench 43.

When the heterojunction is formed due to the contact between thepolysilicon layer 70 and the drain region 54 as in the secondembodiment, on the other hand, a current can be fed to the side of theheterojunction in preference to the side of the body diode 73, even if areverse voltage is applied between the source and the drain and thecurrent can flow to the aforementioned body diode 73. Consequently, thecrystal defect of SiC can be prevented from spreading, and increase inthe on-resistance can be suppressed.

The intermediate layer 71, laminated on the polysilicon layer 70, isformed by a single layer containing Ti (titanium) or a plurality oflayers including the layer. The layer containing Ti can be prepared fromTi, TiN (titanium nitride) or the like. The thickness of theintermediate layer 71 is 200 to 500 nm, for example.

The metal layer 72, laminated on the intermediate layer 71, is made ofAl (aluminum), Au (gold), Ag (silver), Cu (copper) or Mo (molybdenum),an alloy thereof, or a metal material containing the same, for example.The metal layer 72 forms the outermost layer of the source wire 69. Thethickness of the metal layer 72 is 1 to 5 μm, for example.

More specifically, the polysilicon layer 70, the intermediate layer 71and the metal layer 72 may be combined in a multilayer structure(Poly-Si/Ti/TiN/Al) obtained by successively laminating Poly-Si (thepolysilicon layer 70), Ti (the intermediate layer 71), TiN (theintermediate layer 71) and Al (the metal layer 72).

A drain electrode 74 is formed on the rear surface 50 of the SiCsubstrate 42, to cover the overall region thereof. The drain electrode74 is common to all unit cells 44. The drain electrode 74 has amultilayer structure (Ti/Al) obtained by laminating Ti and Alsuccessively from the side of the SiC substrate 42, for example.

A prescribed voltage (a voltage of not less than a gate thresholdvoltage) is applied to the gate pad 48 while a prescribed potentialdifference is caused between the source pad 46 (the source wire 69) andthe drain electrode 74 (between a source and a drain), whereby a channelis formed in the vicinity of the interface between the body region 53and the gate insulating film 63 due to an electric field from the gateelectrode 66. Thus, a current flows between the source wire 69 and thedrain wire 74, and the VDMOSFET is turned on.

FIGS. 5A to 5Q are schematic sectional views for illustrating a methodof manufacturing the semiconductor device 41 shown in FIG. 4 in steporder.

First, an SiC crystal is grown on the surface 49 (the Si surface) of theSiC substrate 42 by epitaxy such as CVD (Chemical Vapor Deposition), LPE(Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping thesame with an impurity, as shown in FIG. 5A. Thus, the N⁻-type epitaxiallayer 51 is formed on the SiC substrate 42.

Then, a P-type impurity is implanted into the epitaxial layer 51 fromthe surface 52 thereof, as shown in FIG. 5B. While the implantationconditions vary with the type of the P-type impurity, accelerationenergy is 200 to 3000 keV, for example.

Then, a mask 75 made of SiO₂ is formed on the epitaxial layer 51 by CVD,as shown in FIG. 5C. Then, the mask 75 is etched through a photoresistfilm (not shown) into a pattern having an opening 76 in a region forforming the body contact region 56. After the formation of the opening76, a P-type impurity is implanted into the epitaxial layer 51 from thesurface 52 thereof. While the implantation conditions vary with the typeof the P-type impurity, acceleration energy is 30 to 400 keV, forexample. After the implantation of the P-type impurity, the mask 75 isremoved.

Then, an N-type impurity is implanted into the epitaxial layer 51 fromthe surface 52 thereof, as shown in FIG. 5D. While the implantationconditions vary with the type of the N-type impurity, accelerationenergy is 30 to 400 keV, for example.

Then, a mask 77 made of SiO₂ is formed on the overall region of thesurface 52 of the epitaxial layer 51 by CVD or thermal oxidation, asshown in FIG. 5E. The mask 77 may alternatively be made of SiN or thelike through CVD. Then, the mask 77 is etched through a photoresist film(not shown) into a pattern having openings 78 in regions for forming thegate trench 43 and the source trench 45. After the formation of theopenings 78, mixed gas (SF₆/O₂ gas) containing SF₆ (sulfur hexafluoride)and O₂ (oxygen) or mixed gas (SF₆/O₂/HBr gas) containing SF₆, O₂ and HBr(hydrogen bromide), for example, is introduced into the surface 52 ofthe epitaxial layer 51 through the openings 78. Thus, the epitaxiallayer 51 is dry-etched from the surface 52 (the Si surface), and thegate trench 43 and the source trench 45 are formed at the same time.Further, the large number of unit cells 44 are formed on the epitaxiallayer 51.

Then, the mask 77 is removed by wet etching, as shown in FIG. 5F.

Thereafter an organic material film 81 is formed on the overall regionof the surface 52 of the epitaxial layer 51, as shown in FIG. 5G. Theorganic material film 81 is made of a material containing carbon, towhich an organic material (polyimide or the like, for example) employedas a photoresist material or the like can be applied, for example. Theorganic material film 81 is formed with a spin coater or the like, forexample.

After the formation of the organic material film 81, the SiC substrate42 is charged into a resistance heating furnace 82. The resistanceheating furnace 82 is not particularly restricted, so far asairtightness in the resistance heating furnace 82 in which a heatedobject is set can be ensured and gas can be introduced thereinto.Further, the heating system of the resistance heating furnace 82 may beeither direct heating or indirect heating.

When the SiC substrate 42 is set in the resistance heating furnace 82,inert gas (N₂, Ar or the like, for example) is introduced into theresistance heating furnace 82, which in turn is subjected totemperature-rise control (first temperature-rise control).

In the first temperature-rise control, the heating temperature iscontrolled to rise from 100° C. to 1000° C. over 35 to 45 minutes, forexample, and thereafter held at 1000° C. (first temperature holding) for5 to 10 minutes, for example, as shown in FIG. 6. Due to the temperaturerise and the temperature holding, elements other than carbon evaporatefrom the organic material film 81, which in turn is altered into acarbon film 83, as shown in FIG. 5H. Therefore, the overall region ofthe surface 52 of the epitaxial layer 51 is covered with the carbon film83.

Then, the resistance heating furnace 82 is subjected to furthertemperature-rise control (second temperature-rise control) while theinner portion thereof is kept in the inert atmosphere.

In the second temperature-rise control, the heating temperature iscontrolled to rise from 1000° C. to 1600° C. over 30 to 60 minutes, forexample, as shown in FIG. 6. After the temperature rise, the heatingtemperature is held at 1600° C. (second temperature holding) for 5 to 10minutes, for example. Due to the temperature rise and the temperatureholding, ions of the individual N- and P-type impurities implanted intoa surface layer portion of the epitaxial layer 51 are activated, and thebody region 53, the source region 55 and the body contact region 56 areformed in response to the implanted portions respectively, as shown inFIG. 5I. Further, the drain region 54 maintaining the state after theepitaxy is formed on a base layer portion of the epitaxial layer 51.

Then, the resistance heating furnace 82 is subjected to temperature-dropcontrol while the inner portion thereof is kept in the inert atmosphere.

In the temperature-drop control, the heating temperature is controlled(temperature-drop-controlled) to drop from 1600° C. to 1300° C. over 15to 30 minutes, for example, as shown in FIG. 6. After the temperaturedrop, nitrogen/oxygen-containing gas is introduced into the resistanceheating furnace 82 for 5 to 10 minutes, for example, while the heatingtemperature is held at 1300° C. (third temperature holding). Due to theintroduction of the nitrogen/oxygen-containing gas, the carbon film 83is oxidized and removed by reacting with oxygen contained in the gas, asshown in FIG. 5J. The introduced nitrogen/oxygen-containing gas can beprepared from gas containing at least N₂O (dinitrogen oxide), and maycontain NO (nitrogen monoxide). The N₂O gas is fed at a flow rate of notmore than 30%, preferably 1 to 30% with respect to the total flow rateof the introduced gas.

Thereafter the heating temperature is further held at 1300° C. (fourthtemperature holding) for 200 to 240 minutes, for example, while thenitrogen/oxygen-containing gas is introduced into the resistance heatingfurnace 82 at the same flow rate. Thus, the surface 52 of the epitaxiallayer 51 is oxidized, and a silicon oxynitride film (the gate insulatingfilm 63) covering the overall region of the surface 52 is formed, asshown in FIG. 5K.

After the formation of the gate insulating film 63, the inert gas (N₂,Ar or the like, for example) is reintroduced into the resistance heatingfurnace 82, while the heating temperature is controlled to drop from1300° C. to 300° C. After the temperature drop, the SiC substrate 42 istaken out from the resistance heating furnace 82.

Then, a doped polysilicon material 84 is deposited from above theepitaxial layer 51 by CVD, as shown in FIG. 5L. The polysilicon material84 is continuously deposited until at least the gate trench 43 and thesource trench 45 are filled up therewith.

Thereafter the deposited polysilicon material 84 is etched back untilthe etched-back surface is flush with the surface 52 of the epitaxiallayer 51, as shown in FIG. 5M.

Then, only the portion of the polysilicon material 84 remaining in thesource trench 45 is removed by dry etching, as shown in FIG. 5N. Thus,the gate electrode 66 is formed by the polysilicon material 84 remainingin the gate trench 43.

Then, the interlayer dielectric film 67 made of SiO₂ is laminated on theepitaxial layer 51 by CVD, as shown in FIG. 5O.

Then, the interlayer dielectric film 67 and the gate insulating film 63are continuously patterned, whereby the contact hole 68 is formed in theinterlayer dielectric film 67 and the gate insulating film 63, as shownin FIG. 5P.

Then, a polysilicon material is deposited by CVD to fill up the contacthole 68, as shown in FIG. 5Q. Thereafter an N- or P-type impurity isimplanted into the deposited polysilicon material. While theimplantation conditions vary with the type of the N- or P-type impurity,acceleration energy is 10 to 100 keV, for example. Thereafter theimpurity is diffused at a temperature of 900° C. for 20 minutes, forexample. Thus, the polysilicon layer 70 doped with the impurity in ahigh concentration is formed. Then, Ti and TiN are deposited in thisorder on the surface of the polysilicon layer 70 by a method such assputtering or vapor deposition, and the intermediate layer 71 is formed.Then, a metal such as Al is deposited on the surface of the intermediatelayer 71 by a method such as sputtering or vapor deposition, and themetal layer 72 is formed. Thus, the source wire 69 is formed. Then, thedrain electrode 74 is formed on the rear surface 50 of the SiC substrate42.

Thereafter the semiconductor device 41 shown in FIG. 4 is obtained byforming the interlayer dielectric film (not shown), the source pad 46and the gate pad 48.

In the semiconductor device 41, as hereinabove described, the sourcewire 69 has the polysilicon layer 70 in the portion in contact with thesource region 55 and the body contact region 56 similarly to thesemiconductor device 1 according to the first embodiment, whereby thesource wire 69 can be brought into ohmic contact with both of the bodycontact region 56 and the source region 55, which are high-concentrationimpurity regions.

When the semiconductor device 41 is manufactured, therefore, a step offorming an Ni layer on the surface 52 of the epitaxial layer 51 can beomitted dissimilarly to a case where a layer made of only a metal suchas Al is directly brought into contact with the impurity regions, and astep of silicifying such an Ni layer can also be omitted. Thus, thesurface 52 of the epitaxial layer 51 can be prevented from formation ofa carbon layer.

Consequently, layer peeling can be suppressed between the source wire 69and the epitaxial layer 51. Thus, connection reliability of the sourcewire 69 can be improved.

Further, the layer (the polysilicon layer 70) entering the source trench45 to come into contact with the drain region 54, the body contactregion 56 and the source region 55 is made of polysilicon excellent incoverage, whereby coverage of the source wire 69 can be improved.Consequently, the connection reliability of the source wire 69 can befurther improved.

In addition, the polysilicon layer 70 is the high-concentration dopedlayer doped with the impurity in the high concentration of 10¹⁹ to 10²¹cm⁻³, whereby the resistance of the source wire 69 can be reduced.

Further, the intermediate layer 71 having the multilayer structure ofthe Ti layer and the TiN layer is interposed between the polysiliconlayer 70 and the metal layer 72. A material containing Ti has excellentadhesiveness with respect to both of a polysilicon material and a metalmaterial. Therefore, adhesiveness between the polysilicon layer 70 andthe metal layer 72 can be improved. Consequently, the connectionreliability of the source wire 69 can be further improved.

In the semiconductor device 41, the source trench 45 is formed at thecenter of each unit cell 44 surrounded by the gate trench 43, wherebycongestion of equipotential lines can be suppressed in the vicinity ofboth end corner portions 61 of the gate trench 43. Consequently, theelectric field applied to both end corner portions 61 on the bottomportion of the gate trench 43 can be relaxed, whereby the portion of thegate insulating film 63 located on the bottom surface 58 can beprevented from dielectric breakdown.

The source trench 45 may be deeper than the gate trench 43, as in asemiconductor device 85 shown in FIG. 7. Thus, the electric fieldapplied to both end corner portions 61 on the bottom portion of the gatetrench 43 can be further relaxed.

FIGS. 8(a) and 8(b) are schematic plan views of a semiconductor deviceaccording to a third embodiment of the present invention, with FIG. 8(a)showing the overall semiconductor device and FIG. 8(b) showing an innerportion thereof in an enlarged manner. Referring to FIGS. 8(a) and 8(b),portions corresponding to those shown in FIGS. 3(a) and 3(b) are denotedby the same reference numerals. In the following, redundant descriptionon the portions denoted by the same reference numerals is omitted.

A semiconductor device 86 according to the third embodiment of thepresent invention is a planar gate power VDMOSFET (an individual device)employing SiC in the form of a chip square in plan view, for example.The chip-like semiconductor device 86 has a length of about several mmin the right-and-left (vertical) direction in the plane of FIG. 8(a).

The semiconductor device 86 has an SiC substrate 42 and a large numberof unit cells 88 formed on the SiC substrate 42 and partitioned by agate electrode 87 latticed in plan view. In other words, the unit cells88 in the form of squares in plan view arranged in window portions ofthe latticed gate electrode 87 respectively are aligned on the SiCsubstrate 42 in the form of a matrix. Each unit cell 88 has a length ofnot more than 10 μm the right-and-left (vertical) direction in the planeof FIG. 8(b), for example, and a source wire 89 is connected to thecenter thereof from the surface side.

FIG. 9 is a schematic sectional view of the semiconductor device 86according to the third embodiment of the present invention, taken alonga line IX-IX in FIG. 8(b). Referring to FIG. 9, portions correspondingto those shown in FIG. 4 are denoted by the same reference numerals. Inthe following, redundant description on the portions denoted by the samereference numerals is omitted.

The sectional structure of the semiconductor device 86 is described withreference to FIG. 9. The semiconductor device 86 includes the SiCsubstrate 41 of an N⁺-type (having a concentration of 10¹⁸ to 10²¹ cm⁻³,for example) and an epitaxial layer 51 laminated on the SiC substrate42.

A large number of well-shaped P-type body regions 90 are formed on theside of the epitaxial layer 51 closer to a surface 52 (an Si surface),with a concentration of 10¹⁶ to 10¹⁹ cm⁻³, for example. A region of theepitaxial layer 51 closer to the side of the SiC substrate 42 (the sideof a C surface) than each body region 90 is an N⁻-type drain region 91(a drift region) maintaining a state after epitaxy.

An N⁺-type source region 92 (having a concentration of 10¹⁸ to 10²¹cm⁻³, for example) and a P⁺-type body contact region 93 (having aconcentration of 10¹⁸ to 10²¹ cm⁻³, for example) surrounded by thesource region 92 are formed in each body region 90.

The latticed gate electrode 87 is formed over the adjacent body regions90, and a gate insulating film 94 is interposed between the gateelectrode 87 and the epitaxial layer 51. The gate electrode 87 extendsover the source region 92 and the drain region 91, to control formationof an inversion layer (a channel) on the surface of the body region 90.The gate insulating film 94 consists of an oxide film containingnitrogen, such as a silicon oxynitride film formed by thermal oxidationwith gas containing nitride and oxygen, for example. The nitrogencontent (the nitrogen concentration) in the gate insulating film 94 is0.1 to 10%, for example.

An interlayer dielectric film 95 made of SiO₂ is laminated on theepitaxial layer 51, to cover the gate electrode 87. In the interlayerdielectric film 95 and the gate insulating film 63, a contact hole 96 isformed in a central region of the body region 90.

A source wire 89 is formed on the interlayer dielectric film 95. Thesource wire 89 collectively enters every contact hole 96, and is incontact with the drain region 91, the body contact region 93 and thesource region 92 in each unit cell 88. In other words, the source wire89 is common to all unit cells 88. An interlayer dielectric film (notshown) is formed on the source wire 89, which in turn is electricallyconnected to a source pad 46 (see FIG. 8(a)) through the interlayerdielectric film (not shown). On the other hand, a gate pad 48 (see FIG.8(a)) is electrically connected to the gate electrode 87 through a gatewire (not shown) drawn onto the interlayer dielectric film (not shown).

The source wire 89 has a polysilicon layer 97, an intermediate layer 98and a metal layer 99 successively from the side in contact with theepitaxial layer 51.

The polysilicon layer 97 is a doped layer made of doped polysilicondoped with an impurity, such as a high-concentration doped layer dopedwith the impurity in a high concentration of 10¹⁹ to 10²¹ cm⁻³, forexample. The impurity for forming the polysilicon layer 97 as the dopedlayer (including the high-concentration doped layer) can be preparedfrom an N-type impurity such as N (nitrogen), P (phosphorus) or As(arsenic) or a P-type impurity such as Al (aluminum) or B (boron). Thethickness of the polysilicon layer 97 is 5000 to 10000 Å, for example.

According to the third embodiment, the polysilicon layer 97 is formed tocover the overall region of the surface of each unit cell 88 exposed inthe contact hole 96, and in contact with the body contact region 93 andthe source region 92.

The layer of the source wire 89 in contact with the body contact region93 and the source region 92 is so made of polysilicon that the sourcewire 89 can be brought into ohmic contact with both of the body contactregion 93 and the source region 92, which are high-concentrationimpurity regions.

The intermediate layer 98, laminated on the polysilicon layer 97, isformed by a single layer containing Ti (titanium) or a plurality oflayers including the layer. The layer containing Ti can be prepared fromTi, TiN (titanium nitride) or the like. The thickness of theintermediate layer 98 is 200 to 500 nm, for example.

The metal layer 99, laminated on the intermediate layer 98, is made ofAl (aluminum), Au (gold), Ag (silver), Cu (copper) or Mo (molybdenum),an alloy thereof, or a metal material containing the same, for example.The metal layer 99 forms the outermost layer of the source wire 98. Thethickness of the metal layer 99 is 1 to 5 μm, for example.

More specifically, the polysilicon layer 97, the intermediate layer 98and the metal layer 99 may be combined in a multilayer structure(Poly-Si/Ti/TiN/Al) obtained by successively laminating Poly-Si (thepolysilicon layer 97), Ti (the intermediate layer 98), TiN (theintermediate layer 98) and Al (the metal layer 99).

A drain electrode 74 is formed on a rear surface 50 of the SiC substrate42, to cover the overall region thereof.

A prescribed voltage (a voltage of not less than a gate thresholdvoltage) is applied to the gate pad 48 while a prescribed potentialdifference is caused between the source pad 46 (the source wire 89) andthe drain electrode 74 (between a source and a drain), whereby a channelis formed in the vicinity of the interface between the body region 90and the gate insulating film 63 due to an electric field from the gateelectrode 87. Thus, a current flows between the source wire 89 and thedrain electrode 74, and the VDMOSFET is turned on.

FIGS. 10A to 10N are schematic sectional views for illustrating a methodof manufacturing the semiconductor device 86 shown in FIG. 9 in steporder. Referring to FIGS. 10A to 10N, portions corresponding to thoseshown in FIGS. 5A to 5Q are denoted by the same reference numerals. Inthe following, redundant description on the portions denoted by the samereference numerals is omitted.

First, an SiC crystal is grown on a surface 49 (an Si surface) of theSiC substrate 42 by epitaxy such as CVD (Chemical Vapor Deposition), LPE(Liquid Phase Epitaxy) or MBE (Molecular Beam Epitaxy) while doping thesame with an impurity, as shown in FIG. 10A. Thus, the N⁻-type epitaxiallayer 51 is formed on the SiC substrate 42.

Then, a mask 39 made of SiO₂ is formed on the epitaxial layer 51 by CVD,as shown in FIG. 10B. Then, the mask 39 is etched through a photoresistfilm (not shown) into a pattern having an opening in a region forforming the body region 90. After the formation of the opening, a P-typeimpurity is implanted into the epitaxial layer 51 from the surface 52thereof. While the implantation conditions vary with the type of theP-type impurity, acceleration energy is 200 to 3000 keV, for example.After the implantation of the P-type impurity, the mask 39 is removed.

Then, a mask 40 made of SiO₂ is formed on the epitaxial layer 51 by CVD,as shown in FIG. 10C. Then, the mask 40 is etched through a photoresistfilm (not shown) into a pattern having an opening in a region forforming the source region 92. After the formation of the opening, anN-type impurity is implanted into the epitaxial layer 51 from thesurface 52 thereof. While the implantation conditions vary with the typeof the N-type impurity, acceleration energy is 30 to 400 keV, forexample. After the implantation of the N-type impurity, the mask 40 isremoved.

Then, a mask 62 made of SiO₂ is formed on the epitaxial layer 51 by CVD,as shown in FIG. 10D. Then, the mask 62 is etched through a photoresistfilm (not shown) into a pattern having an opening in a region forforming the body contact region 93. After the formation of the opening,a P-type impurity is implanted into the epitaxial layer 51 from thesurface 52 thereof. While the implantation conditions vary with the typeof the P-type impurity, acceleration energy is 30 to 400 keV, forexample. After the implantation of the P-type impurity, the mask 62 isremoved.

Thereafter an organic material film 81 is formed on the overall regionof the surface 52 of the epitaxial layer 51, as shown in FIG. 10E.

After the formation of the organic material film 81, the SiC substrate42 is charged into a resistance heating furnace 82. When the SiCsubstrate 42 is set in the resistance heating furnace 82, inert gas (N₂,Ar or the like, for example) is introduced into the resistance heatingfurnace 82, which in turn is subjected to temperature-rise control(first temperature-rise control), similarly to the step shown in FIG. 5H(see FIG. 6). Due to the temperature rise and temperature holding,elements other than carbon evaporate from the organic material film 81,which in turn is altered into a carbon film 83, as shown in FIG. 10F.

Then, the resistance heating furnace 82 is subjected to furthertemperature-rise control (second temperature-rise control) while theinner portion thereof is kept in the inert atmosphere, similarly to thestep shown in FIG. 5I (see FIG. 6). Due to the temperature rise andtemperature holding, ions of the individual N- and P-type impuritiesimplanted into a surface layer portion of the epitaxial layer 51 areactivated, and the body region 90, the source region 92 and the bodycontact region 93 are formed in response to the implanted portionsrespectively, as shown in FIG. 10G. Further, the drain region 91maintaining the state after the epitaxy is formed on a base layerportion of the epitaxial layer 51.

Then, the resistance heating furnace 82 is subjected to temperature-dropcontrol while the inner portion thereof is kept in the inert atmosphere,similarly to the step shown in FIG. 5J (see FIG. 6). Due to thetemperature-drop control introducing nitrogen/oxygen-containing gas, thecarbon film 83 is oxidized and removed by reacting with oxygen containedin the gas, as shown in FIG. 10H.

Thereafter the heating temperature is further held at 1300° C. (fourthtemperature holding) for 200 to 240 minutes, for example, while thenitrogen/oxygen-containing gas is introduced into the resistance heatingfurnace 82 at the same flow rate (see FIG. 6). Thus, the surface 52 ofthe epitaxial layer 51 is oxidized, and a silicon oxynitride film (thegate insulating film 94) covering the overall region of the surface 52is formed, as shown in FIG. 10I.

After the formation of the gate insulating film 94, the inert gas (N₂,Ar or the like, for example) is reintroduced into the resistance heatingfurnace 82, while the heating temperature is controlled to drop from1300° C. to 300° C. After the temperature drop, the SiC substrate 42 istaken out from the resistance heating furnace 82.

Then, a doped polysilicon material 84 is deposited from above theepitaxial layer 51 by CVD, as shown in FIG. 10J.

Thereafter the deposited polysilicon material 84 is removed by dryetching, as shown in FIG. 10K. Thus, the gate electrode 87 is formed.

Then, the interlayer dielectric film 95 made of SiO₂ is laminated on theepitaxial layer 51 by CVD, as shown in FIG. 10L.

Then, the interlayer dielectric film 95 and the gate insulating film 94are continuously patterned so that the contact hole 96 is formed in theinterlayer dielectric film 95 and the gate insulating film 94, as shownin FIG. 10M.

Then, a polysilicon material is deposited by CVD to fill up the contacthole 96, as shown in FIG. 10N. Thereafter an N- or P-type impurity isimplanted into the deposited polysilicon material. While theimplantation conditions vary with the type of the N- or P-type impurity,acceleration energy is 10 to 100 keV, for example. Thus, the polysiliconlayer 97 doped with the impurity in a high concentration is formed.Then, Ti and TiN are deposited in this order on the surface of thepolysilicon layer 97 by a method such as sputtering or vapor deposition,and the intermediate layer 98 is formed. Then, a metal such as Al isdeposited on the surface of the intermediate layer 98 by a method suchas sputtering or vapor deposition, and the metal layer 99 is formed.Thus, the source wire 89 is formed. Then, the drain electrode 74 isformed on the rear surface 50 of the SiC substrate 42.

Thereafter the semiconductor device 86 shown in FIG. 9 is obtained byforming the interlayer dielectric film (not shown), the source pad 46and the gate pad 48.

In the semiconductor device 86, as hereinabove described, the sourcewire 89 has the polysilicon layer 97 in the portion in contact with thesource region 92 and the body contact region 93, whereby the source wire89 can be brought into ohmic contact with both of the body contactregion 93 and the source region 92, which are high-concentrationimpurity regions, similarly to the semiconductor device 1 according tothe first embodiment.

When the semiconductor device 86 is manufactured, therefore, a step offorming an Ni layer on the surface 52 of the epitaxial layer 51 can beomitted dissimilarly to a case where a layer made of only a metal suchas Al is directly brought into contact with the impurity regions, and astep of silicifying such an Ni layer can also be omitted. Thus, thesurface 52 of the epitaxial layer 51 can be prevented from formation ofa carbon layer.

Consequently, layer peeling can be suppressed between the source wire 89and the epitaxial layer 51. Thus, connection reliability of the sourcewire 89 can be improved.

Further, the layer (the polysilicon layer 97) entering the contact hole96 to come into contact with the drain region 91, the body contactregion 93 and the source region 92 is made of polysilicon excellent incoverage, whereby coverage of the source wire 89 can be improved.Consequently, the connection reliability of the source wire 89 can befurther improved.

In addition, the polysilicon layer 97 is the high-concentration dopedlayer doped with the impurity in the high concentration of 10¹⁹ to 10²¹cm⁻³, whereby the resistance of the source wire 89 can be reduced.

Further, the intermediate layer 98 having the multilayer structure ofthe Ti layer and the TiN layer is interposed between the polysiliconlayer 97 and the metal layer 99. A material containing Ti has excellentadhesiveness with respect to both of a polysilicon material and a metalmaterial. Therefore, adhesiveness between the polysilicon layer 97 andthe metal layer 99 can be improved. Consequently, the connectionreliability of the source wire 89 can be further improved.

When the body contact region 93 is formed on a side (a lower portion)closer to the SiC substrate 42 than the source region 92 and a sourcetrench 79 is formed to pass through each body contact region 56 as shownin FIG. 11 similarly to the second embodiment, the polysilicon layer 97can be brought into contact with the drain region 91, the body contactregion 93 and the source region 92 in the source trench 79. In otherwords, a current can be fed to the side of a hetero junction inpreference to the side of a body diode 80 (a PN diode formed by junctionbetween the body region 90 and the drain region 91), even if a reversevoltage is applied between the source and the drain and the currentflows to the body diode 80.

An embodiment related to the invention of a method of manufacturing anSiC semiconductor device through a resistance heating furnace is nowdescribed.

FIG. 12 is a schematic sectional view of a planar gate semiconductordevice.

A semiconductor device 101 has a structure obtained by arranging aplurality of unit cells of a planar gate VDMOSFET in the form of amatrix. FIG. 12 shows only part of the plurality of unit cells.

The semiconductor device 101 includes an N⁺-type SiC substrate 102forming the base of the semiconductor device 101. An N⁻-type epitaxiallayer 103 made of SiC (silicon carbide) doped with an N-type impurity ina lower concentration than the SiC substrate 102 is laminated on asurface 121 of the SiC substrate 102. A surface 131 of the epitaxiallayer 103 is constituted of a (0001) plane of SiC, for example.

An N⁻-type drain region 104 maintaining a state after epitaxy is formedon the epitaxial layer 103.

A P-type body region 105 is formed on a surface layer portion of theepitaxial layer 103. A plurality of such body regions 105 (not shown inFIG. 12) are formed at regular intervals to parallelly extend in thesame direction (a direction perpendicular to the plane of FIG. 12), andarranged in a striped manner or in the form of a matrix, for example.The drain region 104 is exposed between two body regions 105 adjacent toeach other.

On a surface layer portion of the body region 105, an N⁺-type sourceregion 106 is formed at an interval from the peripheral edge thereof.

A gate insulating film 107 extending over the drain region 104, the bodyregion 105 and the source region 106 is formed on the surface 131 of theepitaxial layer 103. The gate insulating film 107 is made of SiO₂.

A gate electrode 108 made of polysilicon doped with an N-type impurityin a high concentration is formed on the gate insulating film 107. Thegate electrode 108 is opposed to the drain region 104, the body region105 and the source region 106 through the gate insulating film 107.

An interlayer dielectric film 109 made of SiO₂ is laminated on theepitaxial layer 103. A source wire 111 is formed on the interlayerdielectric film 109. The source wire 111 is electrically connected tothe body region 105 and the source region 106 through a contact hole 110formed in the interlayer dielectric film 109.

A gate wire 112 is electrically connected to the gate electrode 108through a contact hole (not shown) formed in the interlayer dielectricfilm 109.

A drain electrode 113 is formed on the rear surface of the SiC substrate102.

When the source wire 111 is grounded and the potential of the gateelectrode 108 is controlled while applying a positive voltage of aproper level to the drain electrode 113, a channel can be formed in thevicinity of the interface between the body region 105 and the gateinsulating film 107 due to an electric field from the gate electrode108. Thus, a current can be fed between the source wire 111 and thedrain electrode 113.

FIGS. 13A to 13L are schematic sectional views for illustrating a methodof manufacturing the semiconductor device 101 shown in FIG. 12 in steporder.

First, the epitaxial layer 103 is formed on the surface 121 of the SiCsubstrate 102 by epitaxy, as shown in FIG. 13A. At this time, a majorgrowth surface (the surface 121) of the SiC substrate 102 is defined bya (0001) plane. Due to the surface 121 of the SiC substrate 102 definedby the (0001) plane, the epitaxial layer 103 formed on the SiC substrate102 by epitaxy is grown also with a major surface defined by a (0001)plane. Therefore, the surface 131 of the epitaxial layer 103 parallel tothe surface 121 of the SiC substrate 102 is defined by the (0001) plane.

Then, a photoresist film 114 having an opening 115 in a portion opposedto a region for forming the body region 105 is formed on the surface 131of the epitaxial layer 103 by well-known photolithography. Then, ions(boron ions, for example) of a P-type impurity are introduced into thesurface 131 of the epitaxial layer 103 from above the photoresist film114. Thus, the P-type impurity is implanted into surface layer portionsof portions of the epitaxial layer 103 exposed from the opening 115, asshown in FIG. 13B.

Then, a photoresist film 116 having an opening 117 in a portion opposedto a region for forming the source region 106 is formed on the surface131 of the epitaxial layer 103 by well-known photolithography. Then,ions (arsenic ions, for example) of an N-type impurity are introducedinto the surface 131 of the epitaxial layer 103 from above thephotoresist film 116. Thus, the N-type impurity is implanted into asurface layer portion (closer to the surface 131 than the portions intowhich the P-type impurity has been implanted) of a portion of theepitaxial layer 103 exposed from the opening 117, as shown in FIG. 13C.

After the implantation of the impurity ions into the surface layerportion of the epitaxial layer 103, an organic material film 118 isformed on the overall region of the surface 131 of the epitaxial layer103, as shown in FIG. 13D. The organic material film 118 is made of amaterial containing carbon, to which an organic material (polyimide orthe like, for example) employed as a photoresist material or the likecan be applied, for example. The organic material film 118 is formedwith a spin coater or the like, for example.

After the formation of the organic material film 118, the SiC substrate102 is charged into a resistance heating furnace 122. The resistanceheating furnace 122 is not particularly restricted, so far asairtightness in the resistance heating furnace 122 in which a heatedobject is set can be ensured and gas can be introduced thereinto.Further, the heating system of the resistance heating furnace 122 may beeither direct heating or indirect heating.

When the SiC substrate 102 is set in the resistance heating furnace 122,inert gas (N₂, Ar or the like, for example) is introduced into theresistance heating furnace 122, which in turn is subjected totemperature-rise control (first temperature-rise control).

In the first temperature-rise control, the heating temperature iscontrolled to rise from 100° C. to 1000° C. over 35 to 45 minutes, forexample, and thereafter held at 1000° C. (first temperature holding) for5 to 10 minutes, for example, as shown in FIG. 6. Due to the temperaturerise and the temperature holding, elements other than carbon evaporatefrom the organic material film 118, which in turn is altered into acarbon film 119, as shown in FIG. 13E. Therefore, the overall region ofthe surface 131 of the epitaxial layer 103 is covered with the carbonfilm 119.

Then, the resistance heating furnace 122 is subjected to furthertemperature-rise control (second temperature-rise control) while theinner portion thereof is kept in the inert atmosphere.

In the second temperature-rise control, the heating temperature iscontrolled to rise from 1000° C. to 1600° C. over 30 to 60 minutes, forexample, as shown in FIG. 6. After the temperature rise, the heatingtemperature is held at 1600° C. (second temperature holding) for 5 to 10minutes, for example. Due to the temperature rise and the temperatureholding, ions of the N- and P-type impurities implanted into the surfacelayer portion of the epitaxial layer 103 are activated, and the bodyregion 105 and the source region 106 are formed on the surface layerportion of the epitaxial layer 103, as shown in FIG. 13F. Further, thedrain region 104 isolated from the body region 105 while maintaining thestate after the epitaxy is formed on a base layer portion of theepitaxial layer 103.

Then, the resistance heating furnace 122 is subjected totemperature-drop control while the inner portion thereof is kept in theinert atmosphere.

In the temperature-drop control, the heating temperature is controlled(temperature-drop-controlled) to drop from 1600° C. to 1300° C. over 15to 30 minutes, for example, as shown in FIG. 6. After the temperaturedrop, oxygen-containing gas is introduced into the resistance heatingfurnace 122 for 5 to 10 minutes, for example, while holding the heatingtemperature at 1300° C. (third temperature holding). Due to theintroduction of the oxygen-containing gas, the carbon film 119 isoxidized and removed by reacting with oxygen contained in theoxygen-containing gas, as shown in FIG. 13G. The oxygen-containing gasintroduced into the resistance heating furnace 122 is preferablyprepared from gas containing oxygen and nitrogen. More specifically, gascontaining NO (nitrogen monoxide) or N₂O (dinitrogen oxide) can beemployed.

Thereafter the heating temperature is further held at 1300° C. (fourthtemperature holding) for 200 to 240 minutes, for example, while theoxygen-containing gas is introduced into the resistance heating furnace122. Thus, the surface 131 of the epitaxial layer 103 is oxidized, andan oxide film 120 covering the overall region of the surface 131 isformed, as shown in FIG. 13H.

After the formation of the oxide film 120, the inert gas (N₂, Ar or thelike, for example) is reintroduced into the resistance heating furnace122, while the heating temperature is controlled to drop from 1300° C.to 300° C. After the temperature drop, the SiC substrate 102 is takenout from the resistance heating furnace 122.

Then, a conductive material film is formed by sputtering. Then, theconductive material film is patterned by well-known photolithography andetching, and the gate electrode 108 is formed on the oxide film 120, asshown in FIG. 13I.

Thereafter the interlayer dielectric film 109 is laminated on theepitaxial layer 103 by CVD (Chemical Vapor Deposition), as shown in FIG.13J.

Then, the contact hole 110 is formed in the interlayer dielectric film109 and the oxide film 120 by well-known photolithography and etching,as shown in FIG. 13K. The remaining portion of the oxide film 120 formsthe gate insulating film 107.

Then, a film of a conductive material is formed on the epitaxial layer103 by sputtering. The conductive material is bonded (deposited) to fillup the contact hole 110 and form a thin film on the interlayerdielectric film 109. Then, the conductive material film formed on theinterlayer dielectric film 109 is patterned by well-knownphotolithography and etching. Thus, the source wire 111 is formed, asshown in FIG. 13L. Further, the gate wire 112 electrically connectedwith the gate electrode 108 is formed. In addition, the drain electrode113 is formed on the rear surface of the SiC substrate 102.

The semiconductor device 101 shown in FIG. 12 is obtained through theaforementioned steps.

According to the aforementioned method, the organic material film 118 isheated in the resistance heating furnace 122 by the firsttemperature-rise control after the formation of the organic materialfilm 118 to be altered into the carbon film 119, which is formed on thesurface 131 of the epitaxial layer 103.

After the formation of the carbon film 119, the epitaxial layer 103 isheated due to the second temperature-rise control in the resistanceheating furnace 122 while the inner portion thereof is kept in the inertatmosphere, thereby activating the ions of the N- and P-type impuritiesin the epitaxial layer 103.

Then, the temperature-drop control (temperature drop from 1600° C. to1300° C., for example) is executed while maintaining the resistanceheating furnace 122 in the inert state. Thereafter the oxygen-containinggas is introduced for 5 to 10 minutes, for example, while the heatingtemperature is held at 1300° C. (the third temperature holding). Thus,the carbon film 119 is oxidized and removed, and the surface 131 of theepitaxial layer 103 is exposed.

After the removal of the carbon film 119, the resistance heating furnace122 is subjected to the temperature holding (the fourth temperatureholding) while the oxygen-containing gas is continuously introducedthereinto, whereby the exposed surface 131 is oxidized and the oxidefilm 120 is formed.

The carbon film 119 is formed on the surface 131 of the epitaxial layer103 in advance of the heating (the second temperature-rise control) foractivating the ions, whereby Si escape from the surface 131 can beprevented when the epitaxial layer 103 is heated. Therefore, rougheningof the surface 131 of the epitaxial layer 103 can be suppressed, andplanarity of the surface 131 can be maintained. Consequently, theinterface between the epitaxial layer 103 and the gate insulating film107 can be smoothed, whereby channel mobility of the semiconductordevice 101 can be improved.

Further, the four steps of altering the organic material film 118 intothe carbon film 119 by heating the same (the first temperature-risecontrol), activating the ions by heating the epitaxial layer 103 (thesecond temperature-rise control), oxidizing and removing the carbon film119 with the oxygen-containing gas (the temperature-drop control and thethird temperature holding) and forming the oxide film 120 by oxidizingthe surface 131 of the epitaxial layer 103 (the fourth temperatureholding) can be continuously carried out in the single resistanceheating furnace 122. No apparatus for removing the carbon film 119 orthe like is additionally required, whereby increase in the device costcan also be suppressed. Further, the resistance heating furnace 122 isso employed that the first temperature-rise control, the secondtemperature-rise control, the temperature-drop control as well as thethird temperature holding, and the fourth temperature holding can beprecisely and simply executed.

In addition, the surface 131 of the epitaxial layer 103 on which theoxide film 120 is formed is defined by the (0001) plane, and theoxygen-containing gas introduced into the resistance heating furnace 122is prepared from the gas containing oxygen and nitrogen.

When oxide films are formed by oxidizing (0001) planes of SiC layerswith O₂ gas, H₂O gas (water vapor) and N₂O gas respectively, forexample, MOSFETS including the SiC layers exhibit channel mobilityvalues of 1 to 5 cm²/V·s, 5 to 15 cm²/V·s and 15 to 25 cm²/V·srespectively, for example. In other words, the MOSFET including the SiClayer having the oxide film formed with the N₂O gas is most excellent inchannel mobility.

In the semiconductor device 101 according to the embodiment, the oxidefilm 120 is formed by oxidizing the (0001) plane (the surface 131) ofthe epitaxial layer 103 with NO gas or N₂O gas, whereby the channelmobility of the semiconductor device 101 can be further improved.

EXAMPLES

While the present invention is now described with reference to Exampleand comparative example, the present invention is not restricted by thefollowing Examples.

Example 1

First, an epitaxial layer made of SiC was formed by growing an SiCcrystal on an Si surface of a wafer-shaped SiC substrate (by Cree Inc.).Then, an N-type impurity was multistage-implanted from the surface (theSi surface) of the epitaxial layer with acceleration energy of 30 to 200keV. Thus, an N-type impurity region (having a concentration of 10²⁰cm⁻³) was formed on a surface layer portion of the epitaxial layer.

Then, an insulating film made of SiO₂ was formed on the surface of theepitaxial layer by CVD. Then, a contact hole was formed in theinsulating film, to expose the aforementioned impurity region.

Then, a contact wire was obtained by forming a polysilicon layer bydepositing a polysilicon material in the contact hole by CVD.

Comparative Example 1

Steps similar to those in Example 1 were carried out up to a step offorming a contact hole. After the formation of the contact hole, nickelwas deposited in the contact hole by sputtering. Then, a nickel silicidelayer was obtained by silicifying nickel through a heat treatment at atemperature of 1000° C. Finally, a contact wire was obtained by formingan aluminum layer by depositing aluminum on the nickel silicide layer bysputtering.

1) Photography with Scanning Electron Microscope (SEM)

The contact wires formed according to Example 1 and comparative example1 were scanned with electron beams through a scanning electronmicroscope. SEM images were obtained by image-processing informationdetected by the scanning with the electron beams. FIGS. 14(a) and 14(b)show the SEM images obtained according to Example 1 and comparativeexample 1 respectively.

2) Presence or Absence of Layer Peeling

The presence or absence of layer peeling in the contact wires wasconfirmed by visually recognizing the SEM images shown in FIGS. 14(a)and 14(b).

Referring to FIG. 14(a), the polysilicon layer was in close contact withthe impurity region, and it was confirmable that the polysilicon layerwas excellently in contact with the impurity region. Thus, it has beenconfirmed that connection reliability of the contact wire can beimproved while forming ohmic contact between the contact wire and theimpurity region according to Example 1.

Referring to FIG. 14(b), on the other hand, a void was formed betweenthe nickel silicide layer and the impurity region, and layer peeling wasclearly confirmed therebetween. In other words, a contact failure wasconfirmed between the contact wire and the impurity region.

While the embodiments of the present invention have been described, thepresent invention may be embodied in other ways.

For example, the conductivity types of the semiconductor portions of thesemiconductor device 1, 41, 85 or 86 may be reversed. In other words,the P-type portions may be replaced with N-type portions and vice versain the semiconductor device 1, 41, 85 or 86.

In the semiconductor device 1, only either the source wire 17 or thedrain wire 23 may be employed as the contact wire having the polysiliconlayer.

In the semiconductor device 41, 85 or 86, the contact wire having thepolysilicon layer may be applied to the drain electrode 74.

The crystal planes of the surface 21 or 49 and the rear surface 22 or 50of the SiC substrate 2 or 42 may be reversed. In other words, thesurface 21 or 49 may be a C surface and the rear surface 22 or 50 may bean Si surface in the SiC substrate 2 or 42.

While the contact wire according to the present invention has been shownas the source wire 17 or 69 and the drain wire 23 of the trench gateMOSFET or the source wire 89 of the planar gate VDMOSFET in each of theaforementioned embodiments, the present invention is also applicable toa wire brought into contact with an impurity region of a diode, athyristor or a bipolar transistor, for example.

While the present invention has been described in detail by way of theembodiments thereof, it should be understood that these embodiments aremerely illustrative of the technical principles of the present inventionbut not limitative of the invention. The spirit and scope of the presentinvention are to be limited only by the appended claims.

What is claimed is:
 1. A semiconductor device, comprising: asemiconductor layer made of SiC; a source region of a first conductivitytype formed in the semiconductor layer, the source region forming asurface of the semiconductor layer; a body region of a secondconductivity type formed in the semiconductor layer, the body regionbeing in contact with the source region from a side of a back surface ofthe semiconductor layer; a drain region of a first conductivity typeformed in the semiconductor layer, the drain region being in contactwith the body region from the side of the back surface of thesemiconductor layer; a gate trench dug down in the semiconductor layerfrom the surface thereof, the gate trench passing through the sourceregion and the body region and the deepest portion thereof reaching thedrain region; a gate insulating film formed on an inner surface of thegate trench; a gate electrode embedded in the gate trench on the gateinsulating film; a source trench dug down in the semiconductor layerfrom the surface thereof, the source trench passing through the sourceregion and the body region, and the deepest portion thereof reaching afirst conductivity type part of the drain region; and a conductivematerial embedded in the source trench, the conductive material having afirst layer conforming to a side surface and a bottom surface of thesource trench and a second layer formed on the first layer; wherein thesecond layer includes at least a lower layer conforming to the firstlayer to define a space inside the source trench, and an upper layerembedded in the space.
 2. The semiconductor device according to claim 1,wherein the source trench passes through the source region and the bodyregion and the deepest portion thereof reaches the drain region.
 3. Thesemiconductor device according to claim 1, wherein an ohmic contact isselectively formed between the first layer and the semiconductor layer.4. The semiconductor device according to claim 1, wherein an non-ohmiccontact is selectively formed between the first layer and thesemiconductor layer.
 5. The semiconductor device according to claim 1,wherein the upper layer includes a surface layer made of Al.
 6. Thesemiconductor device according to claim 5, wherein the lower layerincludes an intermediate layer between the first and surface layers. 7.The semiconductor device according to claim 6, wherein the intermediatelayer contains Ti.
 8. The semiconductor device according to claim 6,wherein the intermediate layer contains TiN.
 9. The semiconductor deviceaccording to claim 6, wherein the intermediate layer has a laminatingstructure of Ti and TiN.
 10. The semiconductor device according to claim1, the gate trench and the source trench have the same depth.
 11. Thesemiconductor device according to claim 1, wherein the source trench isdeeper than the gate trench.
 12. The semiconductor device according toclaim 1, wherein the source region is an n⁺-type source region, thedrain region is an n-type drain region, and the body region has a p-typeregion forming a side surface of the gate trench, and a p⁺-type regionforming the side surface of the source trench and having an impurityconcentration larger than that of the p-type region.
 13. Thesemiconductor device according to claim 12, wherein an ohmic contact isselectively formed between the first layer and the n⁺-type sourceregion.
 14. The semiconductor device according to claim 1, wherein thefirst layer is made of polysilicon.
 15. The semiconductor deviceaccording to claim 1, wherein the gate trench is formed to surround thesource trench in plan view.
 16. A semiconductor device, comprising: asemiconductor layer made of SiC; a source region formed in thesemiconductor layer, the source region forming a surface of thesemiconductor layer; a body region formed in the semiconductor layer,the body region being in contact with the source region from a side of aback surface of the semiconductor layer; a drain region formed in thesemiconductor layer, the drain region being in contact with the bodyregion from the side of the back surface of the semiconductor layer; agate trench dug down in the semiconductor layer from the surfacethereof, the gate trench passing through the source region and the bodyregion and the deepest portion thereof the drain region; a gateinsulating film formed on an inner surface of the gate trench; a gateelectrode embedded in the gate trench on the gate insulating film; asource trench dug down in the semiconductor layer from the surfacethereof; and a conductive material embedded in the source trench, theconductive material having a first layer conforming to a side surfaceand a bottom surface of the source trench and a second layer formed onthe first layer; wherein the first layer selectively forms an ohmiccontact and a first junction with respect to the semiconductor layer,the first junction having a smaller junction barrier than the diffusionpotential of a body diode intrinsic in the semiconductor device, andwherein the second layer includes at least a lower layer conforming tothe first layer to define a space inside the source trench, and an upperlayer embedded in the space.
 17. The semiconductor device according toclaim 16, wherein the source trench passes through the source region andthe body region and the deepest portion thereof reaches the drainregion.
 18. The semiconductor device according to claim 16, wherein anon-ohmic contact is selectively formed between the conductive materialand the semiconductor layer.
 19. The semiconductor device according toclaim 16, the gate trench and the source trench have the same depth. 20.The semiconductor device according to claim 16, wherein the sourcetrench is deeper than the gate trench.
 21. The semiconductor deviceaccording to claim 16, wherein the source region is an n⁺-type sourceregion, the drain region is an n-type drain region, and the body regionhas a p-type region forming a side surface of the gate trench, and ap⁺-type region forming the side surface of the source trench and havingan impurity concentration larger than that of the p-type region.
 22. Thesemiconductor device according to claim 21, wherein an ohmic contact isselectively formed between the conductive material and the n⁺-typesource region.
 23. The semiconductor device according to claim 16,wherein the gate trench is formed to surround the source trench in planview.
 24. A semiconductor device, comprising: a semiconductor layer madeof SiC; a source region of a first conductivity type in a surface of thesemiconductor layer; a body region of a second conductivity type formedin the semiconductor layer, the body region being in contact with thesource region from a side of a back surface of the semiconductor layer;a drain region of a first conductivity type formed in the semiconductorlayer, the drain region being in contact with the body region from theside of the back surface of the semiconductor layer; a gate trench inthe semiconductor layer, the gate trench passing through the sourceregion and the body region and the deepest portion thereof reaching thedrain region; a gate insulating film formed on an inner surface of thegate trench; a gate electrode embedded in the gate trench on the gateinsulating film; a source trench in the semiconductor layer, the sourcetrench being deeper than the gate trench; and a conductive material inthe source trench; the conductive material having a first layer and asecond layer formed on the first layer, wherein the second layerincludes at least a lower layer conforming to the first layer to definea space inside the source trench, and an upper layer embedded in thespace, where the lower layer and the upper layer are different materialsfrom each other, the conductive material comprises a polysilicon layer,a non-ohmic contact is selectively formed between the polysilicon layerand a portion of the drain region in the semiconductor layer made ofSiC; and the non-ohmic contact is a heterojunction between thepolysilicon layer and the drain region.
 25. The semiconductor deviceaccording to claim 24, wherein the portion of the drain region islocated at least at a side of the source trench.
 26. The semiconductordevice according to claim 24, wherein the portion of the drain region islocated below the source region.
 27. The semiconductor device accordingto claim 24, wherein the portion of the drain region is located belowthe body region.
 28. The semiconductor device according to claim 24,wherein the conductive material comprises a metal layer.
 29. Thesemiconductor device according to claim 28, wherein the conductivematerial further comprises an intermediate layer at least at a portionbetween the semiconductor layer and the metal layer.
 30. Thesemiconductor device according to claim 29, wherein the intermediatelayer comprises titanium.
 31. The semiconductor device according toclaim 30, wherein the metal layer comprises an aluminum layer.
 32. Thesemiconductor device according to claim 31, wherein the first layer is apolysilicon layer.
 33. The semiconductor device according to claim 24,wherein the conductive material comprises an aluminum layer.
 34. Thesemiconductor device according to claim 24, wherein the conductivematerial comprises a polysilicon layer.
 35. The semiconductor deviceaccording to claim 24, wherein a part of the second layer is connectedto outside of the source trench and is arranged over the gate trench.36. A semiconductor device, comprising: a semiconductor layer made ofSiC; a source region of a first conductivity type in a surface of thesemiconductor layer; a body region of a second conductivity type formedin the semiconductor layer, the body region being in contact with thesource region from a side of a back surface of the semiconductor layer;a drain region of a first conductivity type formed in the semiconductorlayer, the drain region being in contact with the body region from theside of the back surface of the semiconductor layer; a gate trench inthe semiconductor layer, the gate trench passing through the sourceregion and the body region and the deepest portion thereof reaching thedrain region; a gate insulating film formed on an inner surface of thegate trench; a gate electrode embedded in the gate trench on the gateinsulating film; a source trench in the semiconductor layer, the sourcetrench passing through the source region and the body region to reachthe drain region; and a conductive material in the source trench; theconductive material having a first layer and a second layer formed onthe first layer, wherein the second layer includes at least a lowerlayer conforming to the first layer to define a space inside the sourcetrench, and an upper layer embedded in the space, where the lower layerand the upper layer are different materials from each other; theconductive material contacts with the source region at the surface ofthe semiconductor layer, the conductive material comprises a polysiliconlayer, a non-ohmic contact is selectively formed between the polysiliconlayer and a portion of the drain region in the semiconductor layer madeof SiC; and the non-ohmic contact is a heterojunction between thepolysilicon layer and the drain region.
 37. The semiconductor deviceaccording to claim 36, wherein a non-ohmic contact is selectively formedbetween the conductive material and a portion of the drain region in thesemiconductor layer, and the portion of the drain region is located atleast at a side of the source trench.
 38. The semiconductor deviceaccording to claim 36, wherein a non-ohmic contact is selectively formedbetween the conductive material and a portion of the drain region in thesemiconductor layer, and the portion of the drain region is locatedbelow the source region.
 39. The semiconductor device according to claim36, wherein a non-ohmic contact is selectively formed between theconductive material and a portion of the drain region in thesemiconductor layer, and the portion of the drain region is locatedbelow the body region.
 40. The semiconductor device according to claim36, wherein the conductive material comprises a metal layer.
 41. Thesemiconductor device according to claim 40, wherein the conductivematerial further comprises an intermediate layer at least at a portionbetween the semiconductor layer and the metal layer.
 42. Thesemiconductor device according to claim 41, wherein the intermediatelayer comprises titanium.
 43. The semiconductor device according toclaim 36, wherein the conductive material comprises an aluminum layer.44. The semiconductor device according to claim 36, wherein theconductive material comprises a polysilicon layer.
 45. The semiconductordevice according to claim 36, wherein the conductive material comprisesan aluminum layer.
 46. The semiconductor device according to claim 45,wherein the first layer is a polysilicon layer.
 47. The semiconductordevice according to claim 36, wherein a part of the second layer isconnected to outside of the source trench and is arranged over the gatetrench.
 48. The semiconductor device according to claim 36, wherein thesource trench is deeper than the gate trench.